收藏本站
REV. 0
–4–
AD5426/AD5432/AD5443
TIMING CHARACTERISTICS
1
Parameter
3.0 V to 5.5 V
4.5 V to 5.5 V
Unit
Conditions/Comments
f
SCLK
t
1
t
2
t
3
t
42
t
5
t
6
t
7
t
8
t
93
50
20
8
8
13
5
3
5
30
80
120
50
20
8
8
13
5
3
5
30
45
65
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns typ
ns max
Max clock frequency
SCLK cycle time
SCLK high time
SCLK low time
SYNC
falling edge to SCLK active edge setup time
Data setup time
Data hold time
SYNC
rising edge to SCLK active edge
Minimum
SYNC
high time
SCLK active edge to SDO valid
NOTES
1
See Figures 1 and 2.
Temperature range is as follows: Y version: –40
°
C to +125
°
C.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
2
Falling or rising edge as determined by control bits of serial word.
3
Daisy-chain and readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3.
Specifications subject to change without notice.
(V
DD
= 3 V to 5.5 V, V
REF
= 10 V, I
OUT
2 = O V. All specifications T
MIN
to T
MAX
, unless otherwise noted.)
DB15
DB0
t
4
t
8
t
5
t
6
t
2
t
3
t
1
t
7
SCLK
SYNC
DIN
ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.
Figure 1. Standalone Mode Timing Diagram
DB15 (N)
DB0 (N)
DB15
(N+1)
DB0 (N+1)
SCLK
SYNC
SDIN
SDO
ALTERNATiVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.
t
4
t
5
t
6
t
2
t
1
t
3
t
7
t
8
t
9
DB15(N)
DB0(N)
Figure 2. Daisy-chain and Readback Modes Timing Diagram
发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

*型号 *数量 厂商 批号 封装
添加更多采购

我的联系方式

*
*
*
相关PDF资料
EVAL-AD5520EB Per Pin Parametric Measurement Unit/Source Measure Unit
EVAL-AD5532EB 32-Channel, 14-Bit Voltage-Output DAC
EVAL-AD5533EB 32-Channel Precision Infinite Sample-and-Hold
Eval-AD5570EB True Accuracy, 16-Bit 12 V/15 V, Serial Input Voltage Output DAC
EVAL-AD5620EB Single, 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference in SOT-23
EVAL-AD5663REB Dual 12-/14-/16-Bit nanoDAC with 5 ppm/C On-Chip Reference
EVAL-AD5664REB Quad, 12-/14-/16-Bit nanoDACs with 5 ppm/C On-Chip Reference
EVAL-AD5666EB Quad, 16-Bit DAC with 5 ppm/C On-Chip Reference in 14-Lead TSSOP
相关代理商/技术参数
EVAL-AD5443EBZ 功能描述:BOARD EVAL FOR AD5433 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5443SDZ 功能描述:BOARD EVAL FOR AD5443 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5444EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk
EVAL-AD5444EBZ 制造商:Analog Devices 功能描述:EVAL KIT FOR 12-/14BIT HIGH BANDWIDTH MULTIPLYING DACS W/ SE - Bulk
EVAL-AD5445EB 制造商:Analog Devices 功能描述:EVALUATION BOARD - Bulk
EVAL-AD5445EBZ 功能描述:BOARD EVALUATION FOR AD5445 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5445SDZ 功能描述:BOARD EVAL FOR AD5445 RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:* 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581
EVAL-AD5446EB 制造商:Analog Devices 功能描述:EVALUATION BOARD I.C. - Bulk